Riichiro Shirota | Distinguished Professor
National Tsing-Hua University

Riichiro Shirota is a distinguished professor at National Tsing-Hua University, renowned for his groundbreaking research in the field of memory and storage technologies. With over 23 years of experience in the Toshiba corportation in Japan, he has made significant contributions to the development of NAND Flash from 1987. His expertise lies in the design of memory cell operation of NAND Flash, with a focus on improving performance, reliability.

Professor Shirota has a proven track record of leading innovative projects and collaborating with industry partners to bring cutting-edge technologies to market. He is a sought-after speaker at international conferences and has published numerous papers in top-tier journals. His research has been instrumental in shaping the future of memory and storage systems, paving the way for advancements in artificial intelligence, data analytics, and cloud computing.

As a thought leader in the field, Professor Shirota is dedicated to pushing the boundaries of what is possible in memory and storage technologies. His vision for the future includes developing novel solutions that can meet the growing demands of data-intensive applications and enable new possibilities in computing. With his deep knowledge and passion for innovation, Professor Shirota continues to inspire the next generation of researchers and engineers to drive progress in this rapidly evolving field.

Appearances:

Future of Memory and Storage - Day 2 @ 08:35

A Novel 3D Cell Array Architecture for Capacitor less DRAM

A novel three-dimensional (3D) capacitor-less dynamic random-access memory (1T-DRAM) array is proposed as a high-density and high-performance memory solution. The device incorporates a double-gate and stacked-channel architecture to realize a 3D 1T-DRAM array. This Paper has been accepted by IEEE transaction of Electron Device and will be published in 2026. The major advantage is listed as below:

Saving Power Consumption: Refresh time is dramatically increased from 32ms(DDR5)/64ms(DDR4) to 2,900ms at 85℃. DRAM refresh power consumption can be improved 10X or higher level.
Higher bandwidth: Refresh operation will interrupt regular access from DRAM. Since refresh time is increased to 2,900ms then random access bandwidth can be maximized.
Cost of DRAM memory chip: This research can replace 1T-1C DRAM array with 3D 1T-DRAM array. With supporting from 3D NAND fabrication technology, 5-10X cost saving can be achieved compared with 1Z or 1-alpha DRAM technology.
Maximum DRAM density in one chip/package: Currently max single Die DRAM IC is ~32Gb and it is very difficult to increase by 1T-1C DRAM structure. This 3D DRAM technology can achieve 128Gb~512Gb with multiple layers.

ALEX TECHANG TSENG, CEO, IMSolution Co., Ltd.