Kurtis Bowman | Director, Architecture and Strategy
AMD
Kurtis Bowman is a technologist at AMD and Chair of the UALink Consortium, where he helps drive the development of open, high-performance scale-up interconnect standards for next-generation AI and HPC systems. At FMS 2026, Kurtis will present on UALink, an open accelerator interconnect designed to enable low-latency, high-bandwidth communication across large pools of accelerators—an increasingly important capability as AI models, memory demands, and rack-scale architectures continue to grow. UALink’s focus on accelerator-to-accelerator communication, memory sharing, and an open ecosystem makes Kurtis’s session especially relevant for attendees working across AI infrastructure, advanced memory systems, storage, data center architecture, and heterogeneous computing.
Appearances:
Future of Memory and Storage - Day 2 @ 08:50
Rethinking AI Infrastructure: Memory, Storage, and Interconnect as One System
Artificial intelligence has shifted the center of gravity in computing architecture. Performance is no longer defined solely by processor capability, but by how efficiently data moves across accelerators, memory tiers, and storage domains. As models scale from billions to trillions of parameters, traditional boundaries between compute, memory, storage, and networking are dissolving.
This talk examines how emerging AI workloads are reshaping platform design from the rack outward, highlighting the technical and economic forces driving composable memory, accelerator fabrics, and open interconnect ecosystems. It explores why cohesive, multi-vendor system design across silicon, fabrics, and software is essential for sustainable scaling.
Attendees will gain a system-level view of current architectural limits, emerging design patterns, and the critical role open, high-performance interconnects will play in next-generation AI infrastructure.
Future of Memory and Storage - Day 3 @ 08:30
Panel Discussion - Accelerator Fabrics
In current AI-centric architectures, memory is one of the core bottlenecks. While memory vendors work hard to increase density to scale up, memory expansion remains one of the best alternatives to scale out.
While protocols like CXL matured for CPU-centric architectures, the advent of AI factories and the subsequent move to accelerator-centric architectures have opened the door for more alternatives over different interconnects. Examples include NVLink, Infinity Fabric, UALink, and ESUN. Through different trade-offs, all of them are able to support memory semantics, thus enabling different paths to memory expansion.
In this panel, we bring together industry leaders with expertise on each of the fabrics above. They will discuss the pros and cons of each technology, the use cases they target, and the maturity of each approach. The audience will have a unique opportunity to interact and learn from the people building the future of memory expansion.
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