Jai Kumar | Distinguished Engineer
Broadcom

Jai Kumar is a Distinguished Engineer at Broadcom with more than 25 years of experience in networking, systems, and advanced computing technologies. He holds an undergraduate degree in Computer Science and Engineering from IIT Delhi and a graduate degree in Machine Learning from Georgia Tech. Throughout his career, he has been awarded more than 20 issued patents, reflecting his commitment to innovation and technological advancement.

Jai is actively involved in industry standards and open-source networking initiatives and is recognized as one of the top 1% contributors to the OCP community. He has played a significant role in driving the development and adoption of open networking technologies across the industry.

In addition, Jai serves as the Chair of the CSIG and BTS Ad Hoc groups within the UEC. He is a key contributor to several UEC specifications, including CSIG and LLR/CBFC/CSIG SAI specifications, working closely with industry leaders to advance next-generation networking technologies, interoperability, and ecosystem collaboration.

His expertise spans high-performance networking, AI infrastructure, cloud-scale systems, and industry standardization, making him a respected leader in the networking community.

Appearances:

Future of Memory and Storage - Day 3 @ 08:30

Panel Discussion - Accelerator Fabrics

In current AI-centric architectures, memory is one of the core bottlenecks. While memory vendors work hard to increase density to scale up, memory expansion remains one of the best alternatives to scale out.

While protocols like CXL matured for CPU-centric architectures, the advent of AI factories and the subsequent move to accelerator-centric architectures have opened the door for more alternatives over different interconnects. Examples include NVLink, Infinity Fabric, UALink, and ESUN. Through different trade-offs, all of them are able to support memory semantics, thus enabling different paths to memory expansion.

In this panel, we bring together industry leaders with expertise on each of the fabrics above. They will discuss the pros and cons of each technology, the use cases they target, and the maturity of each approach. The audience will have a unique opportunity to interact and learn from the people building the future of memory expansion.

Moderator: J Metz, Director & Chair, Ultra Ethernet Consortium, AMD & SNIA