J is Technical Director for Systems Design for AMD where he works to coordinate and lead strategy on various industry initiatives related to systems architecture, including advanced networking and storage. He has a unique ability to dissect and explain complex concepts and strategies, and is passionate about the inner workings and application of emerging technologies.
Artificial intelligence has shifted the center of gravity in computing architecture. Performance is no longer defined solely by processor capability, but by how efficiently data moves across accelerators, memory tiers, and storage domains. As models scale from billions to trillions of parameters, traditional boundaries between compute, memory, storage, and networking are dissolving.
This talk examines how emerging AI workloads are reshaping platform design from the rack outward, highlighting the technical and economic forces driving composable memory, accelerator fabrics, and open interconnect ecosystems. It explores why cohesive, multi-vendor system design across silicon, fabrics, and software is essential for sustainable scaling.
Attendees will gain a system-level view of current architectural limits, emerging design patterns, and the critical role open, high-performance interconnects will play in next-generation AI infrastructure.