Jason Jung | Principal Engineer
Micron

Jason Jung is a Principal Hardware Engineer in Micron’s TPG Pathfinding Storage and Memory Systems Group (Richardson, Texas, USA). He has over 25 years of experience in scale-up chipset design, disaggregated memory systems, and near-memory compute. He earned a B.S. in Computer Engineering from Texas A&M University (College Station, TX). He is currently leading a hardware emulation project to evaluate high-IOPS storage solutions for AI workloads.

Appearances:

Future of Memory and Storage - Day 2 @ 08:35

Disaggregated 16 TB Shared Memory System for AI and Science Applications

Micron and the Department of Energy’s Pacific Northwest National Laboratory (PNNL) have collaborated to build a multi-host, 12-terabyte disaggregated, tiered, and shared memory prototype system with near memory compute capabilities. Recently deployed at PNNL in Richland, Washington, the system is supporting AI and broader research workloads of several DOE labs.

This presentation will describe the system topology and the key technical challenges encountered while building a reconfigurable shared-memory system. In particular, it addresses how CXL 3.x shared-memory features were enabled in a CXL 2.x environment. The presentation will also include the solutions developed to ensure memory coherency and the software required to run applications on the host processors as well as on the processors embedded in the memory devices. Some practical software performance acceleration numbers will also be presented.

Skyler Windh, Member of Technical Staff Systems Software Engineering, Micron