Bill Gervasi | Principal Memory Solutions Architect
Monolithic Power System
Mr. Gervasi has nearly 5 decades of experience in high speed memory subsystem definition, design, and product development. He piloted the definition of Double Data Rate SDRAM since its earliest inception, authoring the first standard specification, and created the Automotive SSD standard. With MPS, Bill is driving some of the memory and storage system management mechanisms for a post-quantum world. He received the JEDEC Technical Excellence award, their highest honor, in 2020.
Appearances:
Future of Memory and Storage - Day 1 @ 08:30
Chair's Remarks
Chair's Remarks
Future of Memory and Storage - Day 1 @ 10:30
Data Center Telemetry – Applying AI to Predict Failures
Telemetry gathering during system runtime allows systems managers to track not just the health of their systems, but allows for predicting some future failures before they happen. This trend is entering the memory domain. With health metrics combined with telemetry processing, systems can correlate seemingly disparate factors such as device temperature, access patterns, correctable and uncorrectable errors, post package repair, and use long term logging procedures to connect the dots on these factors. This talk examines trends in adding metrology to systems to enhance system health and reduce costs.
Future of Memory and Storage - Day 1 @ 11:40
FMS Lifetime Achievement Award
Future of Memory and Storage - Day 1 @ 15:30
DRAM Part 1: Fundamentals, From Cells to Modules
The industry has been dealing with “The Memory Wall” for a long time as the advancement of memory has failed to keep up with advancements in processing.
The basic structure of the DRAM core cell is fundamentally unchanged for the last 50 years, so what tricks has the industry pulled to keep DRAM as the basis for all computing?
There are many markets for memory from cell phones to laptops to edge communications nodes to mainframe servers. How is DRAM configured differently so that the same memory chip can be used by all these markets?
Future of Memory and Storage - Day 1 @ 16:30
DRAM Part 2: Systems Implications, Low Power, and HBM Alternatives
- Data centers are grossly inefficient, mostly moving data around rather than processing it.
- Explosion of AI is changing the profile, especially in power consumption.
- There are a few ideas about how to minimize wasted data movement.
- There are ideas about how to place memory fragments near data processors.
- Emergence of quantum computing is challenging how we secure data.
Future of Memory and Storage - Day 2 @ 09:05
DRAM Fundamentals, From Cells to Systems
Understanding computer memory architectures and tiers starts with analyzing the internal workings of the memory devices to understand how they store information, the challenges with maintaining that information, and how to get that data in and out of the attached system. As data rates have increased, new techniques have been developed to ensure data reliability and keep power under control.The majority of memory is assembled onto carriers called DIMMs which come in a variety of configurations based on the application. This training will compare and contrast the families of DIMMs.Takeaways from this session:
- Understand the internal structure of DRAM, how DDR5 evolved from past implementations – and how things stalled to create the Memory Wall
- See how module requirements drive DRAM architecture, and where the RAS-CAS protocol came from
- Understand the many configurations of memory modules
- Understand systems integration of the variety of memory solutions
- Understand how AI is driving new demands for system memory, including both DDR and LPDDR memories
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