Sowmya Rao Panuganti | Associate Director, Memory Solutions Team
Samsung Electronics

Sowmya Rao Panuganti, Associate Director, Memory Solutions Team, Samsung Electronics

Sowmya Rao Panuganti is an Associate Director in Samsung Electronics’ Memory Solutions team. She leads the pre‑silicon validation group that qualifies a wide range of Enterprise and Client NVMe, SAS, and CXL controllers. With more than 18 years of experience, she began as a Validation Test Engineer and progressed to a leadership role, leveraging deep expertise in storage protocols to turn customer use cases into clear technical requirements. She has built and motivated cross‑functional teams that successfully validated many NVMe and SAS controllers, earning several Samsung collaboration awards for aligning diverse groups with organization‑wide delivery goals. Prior to Samsung, Sowmya worked at PMC‑Sierra (IDT). She holds a Master’s degree in Electrical Engineering from the University of Toledo, Ohio.

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Future of Memory and Storage - Day 1 @ 10:20

AI-Based Predictive Hot Page Placement in CXL Memory Systems

CXL enables scalable, cache-coherent memory expansion beyond DRAM. Conventional management treats CXL as a uniform extension, relying on reactive page migration based on access patterns. This identifies hot pages only after performance degradation, failing to prioritize latency-critical data and causing inefficient tiering. We introduce an AI-driven, proactive hot page placement framework that predicts memory demands, enabling early placement of hot pages into DRAM. To ensure real-time operation, we use XGBoost—a lightweight model running on CPU cores—avoiding GPU overhead and enabling nanosecond inference. For dynamic workloads, a feedback loop refines predictions using performance counters, ensuring adaptability without manual tuning. For stability, the framework integrates with kernel tracing and a CXL-aware allocator, using existing OS mechanisms without major modifications. By proactively placing critical pages in DRAM and warm/cold pages in CXL, the system minimizes latency, improves throughput and stabilizes tail latency. This optimizes resource utilization in latency-sensitive environments like real-time databases, gaming, and AI inference, unlocking CXL's full potential

last published: 19/May/26 18:25 GMT

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