Siamak Tavallaei | Sr. Principal Engineer
Samsung Semiconductor, Inc.

Siamak Tavallaei, Sr. Principal Engineer, Samsung Semiconductor, Inc.

Mr. Tavallaei is a seasoned systems architect and technology strategist with over three decades of leadership in memory systems, interconnect technologies, and hyperscale infrastructure. He currently serves as Senior Principal Engineer at Samsung Semiconductor Inc. and CXL Consortium Board Director. His career spans influential roles at Google Cloud (Chief Systems Architect), Microsoft Azure (Principal Engineer), HP (Distinguished Technologist), and Compaq (Principal Member Technical Staff). His projects have generated over 50 patents in server architecture, disaggregated computing, and fault management. He is a long-standing contributor to Open Compute Project (OCP), where he co-led the Server Project. He co-authored specifications for Microsoft’s HGX-1, Project Olympus, DC-SCM, and OAM/OAI, and led the development of DC-MHS for datacenter-ready systems. His work with the Composable Memory Systems (CMS) subproject integrates infrastructure software for memory fabrics serving disaggregated and scale-up AI/ML systems. He frequently shares his insights through mentoring and industry presentations, and his contributions have been recognized by InfiniBand, CXL, and OCP organizations.

Appearances:



Future of Memory and Storage - Day 2 @ 09:20

Modular Software Infrastructure for Composable Memory over Fabrics

As a “Composable Memory Ecosystem Driver,” this presentation includes the outline of a set of modular contributions to promote broad utility and adoption. It uses a jigsaw puzzle model to define input and output (North and South and sideways) APIs for various building blocks. It forms a Base Specification for an architectural blueprint of how various layers interconnect. It includes discovery and enumeration, CXL Fabric Manager, RAS module, Security module, Telemetry, Diagnostics, Dynamic Allocation Policy Manager, Memory Tiering, Memory Pooling, Memory Sharing "Objects,“ Guest OS, and applications. For ease of collaboration and open contribution, it promotes independent building block. This model is extensible to scale-up memory fabrics using different underlying Physical, Link, and Protocol layers.  Based on this Base Specification, we expect the OCP community to contribute several Design and Product Specifications to streamline market adoption of these fabric technologies.

Future of Memory and Storage - Day 2 @ 09:45

Panel Discussion – Scale Up and Scale Out Fabrics for AI

last published: 19/May/26 18:25 GMT

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