Shyam Sharma | Distinguished Engineer
Cadence Design Systems
Shyam has over 26 years of experiences in various fields of Electronic Design Automation. His area of expertise includes processor architecture, interconnects, storage, and memory sub systems. He is currently working as Distinguished Engineer responsible for the entire memory sub system Verification IP product solutions offered by Cadence. He has 2 patents and 25+ papers/posters presentation published to international conferences. He has worked at Mentor Graphics and Denali Design Systems before joining Cadence Design Systems in 2010..
Appearances:
Future of Memory and Storage - Day 2 @ 09:20
Analog features and training modes modelling in digital simulation for memory devices
As high‑speed memory interfaces such as DDR, LPDDR, and HBM become ubiquitous in modern SoCs, increasing I/O speeds, reduced interface voltages, and multiple power rails have made analog behavior a critical aspect of memory verification. While true analog simulation is prohibitively resource‑intensive, purely digital verification is insufficient to capture real device behavior. This work presents an approach for modeling key analog features/trainings within digital memory models to enable early detection of design issues and improve robustness of DDR PHY/memory controller designs. The methodology incorporates digital representations of analog effects such as signal drift, data eye timing, dynamic voltage and frequency scaling , on‑die termination (ODT), Device Feedback equivalization (DFE), ZQ calibration, signal strength, training algorithms, and temperature‑based derating, implemented within C/C++‑based verification IP using standard VPI/DPI interfaces. These models address limitations in specifications and HDLs by providing configurable, timing‑aware checks that expose critical issues—such as incorrect impedance settings or insufficient eye margin missed by conventional model
Future of Memory and Storage - Day 2 @ 15:35
Analytical Framework for Optimal Sample Point Delay Calculation for Signal I/O Buffers
Source-synchronous I/O buffers must determine optimal sampling delays to capture strobe-sampled data reliably. Current training algorithms depends on brute force exhaustive training sweeps that offer no analytical insight. This paper derives an intuitive parameterize template for computing optimal sample point delay from three intuitive timing components—duty cycle centering, channel skew, and receiver offset. The formula uses technology-agnostic symbols and applies to any source-synchronous interface used in typical DRAM based memory subsystems (DDR5, LPDDR, GDDR, HBM) by substituting the relevant specification parameters. We also present specific examples of usages of this approach for Validation on DDR5 Data Buffer configurations from DDR5-3200 through DDR5-12800 that demonstrate accuracy within 2 delay units of empirically trained values.
Beyond theoretical contribution, the framework offers immediate practical value: verification and design engineers can directly program the computed delay to bypass training entirely in simulation or first silicon bring-up, use it as an optimal training seed to reduce sweep range by more than half and convergence time by ∼60%.
Future of Memory and Storage - Day 2 @ 15:50
Comprehensive Coverage Framework for LPDDR6 Feature Validation: Navigating Complex Modes and Reducing the Verification Closure G
LPDDR6's is a breakout DRAM with advanced features—Efficiency Mode, Meta Data on Data Bus, X6 Mode, System Meta Mode including carved-out memory, PRAC, dynamic frequency scaling just to name few—create complex verification challenges beyond traditional Commands, data, Timings, Registers and DRAM state machine coverage. Feature interactions and configuration-dependent behaviors generate exponential scenario spaces that conventional approaches inadequately address. This paper presents a feature-centric coverage framework employing Randomization to generate targeted bins across mode transitions, operating speeds, bus width and density variations. Our coverage framework leverages some of the in-house AI tools to parse specifications and detect coverage gaps which are used for targeted testcase creation. This methodology significantly improves coverage closure and reduces manual effort, providing a scalable solution for validating complex next-generation memory protocols.
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