Shimeng Yu is the endowed Dean’s Professor of Electrical and Computer Engineering at the Georgia Institute of Technology. He received a PhD degree from Stanford University in 2013. He is an elevated IEEE Fellow for contributions to non-volatile memories and in-memory computing. Prof. Yu’s general research interests are emerging devices and 3D integrated circuits for AI hardware. Among Prof. Yu’s recent honors, he was a recipient of Intel Outstanding Researcher Award in 2023, and Semiconductor Research Corporation (SRC) Rama Divakaruni Technical Excellence Award in 2025. Prof. Yu’s 500+ journal/conference publications received more than 40,000 citations (Google Scholar) with H-index 89. For the past decade, Prof. Yu has served as technical program committee and frequent short course/tutorial speakers for the leading conferences in the field, including IEEE International Electron Devices Meeting (IEDM), IEEE Symposium on VLSI Technology and Circuits, IEEE International Memory Workshop (IMW), and IEEE International Reliability Physics Symposium (IRPS), etc. He also has served as an editor for IEEE Electron Device Letters (EDL).
The explosive growth of AI and data-centric computing is creating unprecedented demand for higher DRAM density and energy efficiency. Conventional 6F² DRAM based on buried channel array transistors (BCAT) is approaching fundamental scaling limits at the 0a node, facing pattern distortion, bitline–storage node interference, row hammer vulnerability, and limited cell capacitance. These challenges mark an industry inflection point toward 4F² vertical channel transistor (VCT) architectures, with initial market introduction of sub-10nm 4F² DRAM generations anticipated within the next two years.
This tutorial provides a roadmap-oriented perspective on next-generation DRAM scaling. It first explains how 4F² designs relax 2D layout constraints, simplify structures through shared back-gates, and enhance reliability. Building on 4F² designs, the tutorial introduces CMOS-bonded-array (CBA) integration and its implications for sensing schemes and peripheral routing. This talk also introduces an open DRAM model—historically lacking in the research community—to enable design-technology co-optimization for future DRAM core and peripheral integration under CBA architecture. As a case study, research is performed to study the direct bitline-to-bitline coupling and severe read disturb in 4F² designs. To address this challenge, mitigation strategies such as twisted bitline sense amplifier (BLSA) are proposed and validated by the open DRAM model.