Sean Lin | Technical Manager
Phison Technology
Sean Lin (Yu-Hsiang Lin) is R&D Manager at Phison, where he leads development and research of error correction codes and high-speed DSP implementations. With over 10+ years of experience, he has developed multiple generations of LDPC solutions for embedded, consumer, automotive and enterprise products. His research spans ECC algorithms, VLSI and system architectures, and PAM4 ADC-based DSP in SerDes. He earned his MS in Electrical Engineering from National Chiao Tung University. He holds over 60 granted patents worldwide.
Appearances:
Future of Memory and Storage - Day 1 @ 08:35
Enabling Ultra-High-IOPS Storage-Next SSDs with AI-Enhanced LDPC
Artificial intelligence is reshaping every layer of the computing stack, as well as the storage and memory hierarchy. To meet emerging AI workloads, NVIDIA has introduced the Storage-Next architecture, adding a new tier focused on ultra-high-IOPS random-access performance for small 512-byte I/Os. In this work, we address the key challenges that conventional SSD controllers face in achieving the theoretical maximum PCIe bandwidth with small block sizes. An advanced error-correction scheme tailored for fine-grained, latency-critical storage is essential to transform today’s SSDs into Storage-Next-ready devices. With this advancement, we demonstrate exceptionally low latency while delivering robust reliability. Additionally, we introduce neural network (NN)-assisted LDPC error correction, highlighting the potential of AI-powered approaches to enhance ECC reliability in next-generation AI storage and memory systems.
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