Prashant Dixit | Architect
Siemens EDA

Future of Memory and Storage - Day 3 @ 09:15

Unified Verification Framework for Diverse UCIe Multi-Protocol Implementations

The contemporary landscape of multi-die systems is characterized by rapid advancements and intricate integrations, encompassing a wide array of protocols (e.g., PCIe, CXL, AXI, CHI, UALink, Memories) and interfaces (e.g., C2C, CXS). The strategic adoption of on-package integration, coupled with the performance advantages afforded by UCIe, necessitates a comprehensive and holistic system-level verification strategy for chiplet designs. This approach is critical for meticulously addressing synchronization issues, mitigating timing variations, and ensuring robust protocol interoperability, thereby guaranteeing optimal performance, fortified security, and inherent system stability. We will discuss the architecture of a versatile adapter engineered to facilitate the seamless integration of disparate protocol layers within a UCIe verification environment. This solution streamlines the development and execution of system-level verification TB. Empirical validation through multiple design implementations will be presented, demonstrating the architecture's efficacy in enabling the reuse of existing protocol testbenches with minimal adaptation for UCIe-specific verification requirements.

Prashant Dixit, Architect, Siemens EDA

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Prashant Dixit / Unified Verification Framework for Diverse UCIe Multi-Protocol Implementations

Prashant Dixit, Architect,
Siemens EDA

Prashant Dixit, Architect, has overall 20 years of experience in design and verification industry and is currently working in developing the verification solutions for UCIe at Siemens EDA. He also manages the Verification IPs team which deals with the development, testing and deployment of...

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