Po-Chun Wang | Senior VIP Developer
Siemens Digital Industries Software
Po-Chun is a Senior Engineer at Siemens EDA and a member of the Siemens Avery VIP team, specializing in PCIe and Compute Express Link (CXL) IC design verification. With over five years of experience in Verification IP (VIP) development, he focuses on PCIe/CXL protocol technologies and collaborates closely with IC design customers to deliver advanced verification solutions.
Appearances:
Future of Memory and Storage - Day 2 @ 09:50
Comprehensive Verification of the CXL Hot-Range Monitoring Unit (CHMU) for Reliable Hot Memory Detection
Efficient memory utilization is critical for scalability and performance in HPC data centers and AI servers. Accurate memory monitoring serves as a foundational capability underpinning nearly all memory management and performance optimization frameworks. Recent revisions of the Compute Express Link (CXL) specification introduce the CXL Hot-range Monitoring Unit (CHMU), a standardized interface that enables detection of frequently accessed memory regions with minimal host performance overhead through configurable granularity, epoch control, and hotlist-based reporting.
In this presentation, we will first provide a concise architectural overview of CHMU, including its counter model, epoch configuration, and hotlist management mechanism. We will then introduce a systematic verification methodology that addresses complex configuration dependencies, corner-case analysis, overflow handling, and each reporting mode validation. Through practical error scenarios and validation strategies, this session outlines a structured approach to ensuring accurate, robust, and standards-compliant hot memory monitoring in CXL systems.
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