Peter Graumann | Technical Fellow
Microchip Technology
Peter Graumann has been working in the communications industry for over 35 years. He was a co-founder of two successful startups, Siworks in 1998 and Rad3 Communications in 2008. Peter has worked on high-speed communications systems focusing on PHY processing and Forward Error Correction (FEC) methods for many different channel types including wireless, wired, Fiber Optics and storage. Peter holds over 50 patents and is currently working as a Technical Fellow focusing on FEC and Serdes solutions at Microchip Technology.
Appearances:
Future of Memory and Storage - Day 3 @ 09:20
SSD Error Correction Optimization for AI workloads
The current generation of SSDs operate on 4kByte block boundaries resulting in reads and writes to Flash devices being organized around this size of information block. AI workloads operate on smaller granularities than the traditional 4k Byte SSD FEC block often operating on 512B or 1k Byte blocks of information. At the same time read latency for AI operation must be as small as possible. These smaller blocks must have low latency without sacrificing error correction strength.We present a novel block structure that supports low latency reading and decoding for AI workloads along with a decoding procedure that also provides excellent error correction performance. The forward error correction method supports fast small block reads and decodes, a second layer of hard-decision decoding, and also supports multi-read soft decoding to recovery any high-error blocks from the Flash.
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