Nilesh Shah | VP Business Development
ZeroPoint Technologies
Nilesh Shah is VP of Business Development at ZeroPoint Technologies, focused on AI-era memory efficiency. He advises emerging compute platforms, GPU cloud initiatives, and next-generation storage architectures, and serves as an advisor to the Xcelerated Compute Show and to venture capital firms investing in AI infrastructure.
An active contributor within OCP, SNIA, the CXL Consortium, and JEDEC communities, he is a frequent panelist and moderator at global data center and semiconductor conferences. He previously led data center SSD strategy and high-performance product planning initiatives at a major semiconductor company.
Appearances:
Future of Memory and Storage - Day 1 @ 09:45
Panel Discussion – Storage as a Service: Neo-Cloud Economics vs Hyperscale Control
AI NeoClouds are racing to differentiate but storage margins often flow upstream. Hyperscalers increasingly bundle Storage-as-a-Service with GPU compute, capturing performance premiums and tightening ecosystem control. Meanwhile, scale-out storage platforms (Weka, VAST Data, DDN, Hammerspace) power NeoCloud clusters, abstracting flash volatility while competing on throughput and latency guarantees.Beneath them sit controller, NVMe, and flash suppliers whose economics depend on density, endurance, and bandwidth scaling. Open-source stacks and bare-metal storage clusters offer an alternative path but with operational trade-offs.This panel maps the full stack: hyperscale services, NeoCloud offerings, software, defined storage layers, component vendors, and flash technology providers, asking who owns margin, who owns performance, and how AI-era storage models evolve.
Future of Memory and Storage - Day 2 @ 15:35
Quantum Memory vs Classical Memory: Disruption or Convergence?
Quantum computing is moving into data centers, but its memory stack looks fundamentally different. Quantum memories operate at telecom wavelengths, interface with photonic interconnects, and require cryogenic or hybrid packaging environments. Startups are developing telecom-integrated quantum memory modules designed for long-coherence storage and quantum networking , not byte-addressable DRAM semantics.
Should classical memory and storage providers care? Can DRAM, NAND, MRAM, and CXL vendors extend into quantum control, buffering, or hybrid integration , or is this an entirely new materials and fab ecosystem?
This panel debates whether quantum memory becomes a niche scientific layer or a parallel memory hierarchy with its own fabs, packaging, and telecom integration requirements. As AI and quantum converge, the question is strategic: adapt, partner, or risk irrelevance?
Future of Memory and Storage - Day 3 @ 10:35
Future AI Inference Architectures: Memory-Centric Systems and Emerging Data Center Paradigms
AI infrastructure is shifting from training-heavy, compute-bound systems to inference-dominated deployments constrained by memory bandwidth, capacity, data movement, and power. As model weights, embeddings, and KV caches expand, architectural innovation is moving beyond traditional GPU scaling toward wafer-scale systems, memory-first dataflow accelerators, chiplet-based inference ASICs, and inference-specialized designs.
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