Mao-Ruei Li | Project Deputy Manager
Silicon Motion Inc.

Future of Memory and Storage - Day 1 @ 08:50

Fine Grain ECC Chunk for Fine Grain (512B+) IOs

Emerging Storage-Next architectures, exemplified by NVIDIA’s vision of 100 M random read IOPS with 512-byte granularity, are redefining the performance requirements of solid-state storage. While such throughput will likely be delivered through multi-device aggregation, maximizing the IOPS capability of each individual SSD remains essential for scalability, efficiency, and tail-latency control.Achieving this level of fine-grained performance requires fundamental changes across the SSD stack, from host interfaces to controller processing and internal data paths. Many of these challenges can be addressed through architectural scaling. The most stringent constraints, however, arise at the NAND interface, where array read granularity, data transfer unit, and error-correction granularity must be carefully aligned to sustain extreme random access rates without compromising latency predictability.The primary limitation of BCH lies in its lack of native soft-decision decoding, which raises concerns for long-term reliability under intensive, memory-like access patterns, even when operating with SLC or pseudo-SLC NAND.

Mao-Ruei Li, Project Deputy Manager, Silicon Motion Inc.

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Mao-Ruei Li / Fine Grain ECC Chunk for Fine Grain (512B+) IOs

Mao-Ruei Li, Project Deputy Manager,
Silicon Motion Inc.

Mao-Ruei Li is a Project Deputy Manager of Storage Research Department II at Silicon Motion. Prior to this role, he focused on a VLSI architecture of SERDES. He received the Ph.D. Degrees in electrical engineering from Nation Tsing Hua University. His research in high speed SERDES and error...

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