Khurram Malik is a seasoned technology leader and product marketing executive at Marvell, where he leads the memory and storage subsystem product portfolio. His focus spans some of the most transformative technologies shaping modern infrastructure - including custom HBM (High Bandwidth Memory), disaggregated memory, and CXL (Compute Express Link) solutions. With deep expertise at the intersection of silicon innovation and datacenter architecture, Khurram works closely with hyperscale, enterprise, and cloud customers to accelerate the adoption of next-generation memory technologies. He is a recognized voice in the industry on topics including memory and storage disaggregation, AI infrastructure scaling, and the evolving role of CXL in enabling composable, high-performance data centers. At Marvell, Khurram plays a pivotal role in translating complex technology roadmaps into compelling market strategies - bridging engineering innovation with real-world customer impact.
As AI and data‑intensive workloads continue to scale, conventional memory architectures are increasingly constrained by limitations in capacity, bandwidth, and efficiency. Compute Express Link (CXL) enables a new class for memory‑centric system design through expansion, pooling, and sharing across heterogeneous compute resources.
This session explores how CXL is reshaping system architecture by decoupling memory from compute and enabling more flexible, composable infrastructures. We will examine the key technical challenges and design considerations—including bandwidth management, coherency, and system scalability—and how they impact real‑world cloud and AI deployments.
Attendees will gain insight into how CXL can unlock more efficient resource utilization and support the transition to scalable, high‑performance memory architectures designed for the next generation of data‑driven workloads.
Following our previous presentation at OCP, we have advanced our ASIC-based CXL-PNM initiative through collaboration with SoC partners, evolving the architecture toward a general-purpose core–based ASIC CXL-PNM platform. This approach extends beyond fixed-function acceleration by embedding programmable compute within a CXL-attached device, enabling flexible offload for memory-intensive and data-centric workloads.In this talk, we will present the architectural evolution and representative use cases spanning data analytics, AI data processing, and memory-bound applications. More importantly, we aim to expand collaboration with researchers and industry partners in areas such as workload co-design, system software enablement, and standards-aligned innovation. Through sharing validated results and open research challenges, we seek to foster a broader ecosystem around CXL-PNM.