Helia Naeimi is a Fabric Technologist for Astera Labs. She has 10+ years’ experience including deep computer and networking expertise, with a strong track record of developing product architecture specifications and architecting novel networking accelerator solutions. Prior to Astera Labs, Helia held engineering leadership roles at Meta, Tenstorrent, and Intel. She holds a Ph.D. and an M.S. in Computer Science from the California Institute of Technology, and a B.S. in Computer Engineering from Sharif University of Technology.
As AI workloads grow exponentially, traditional interconnects—designed for scale-out or proprietary deployments—are struggling to keep pace with the bandwidth, latency, and scalability demands of next-generation AI systems.
UALink is an open, memory-semantic fabric purpose-built for scale-up architectures, enabling direct memory access and atomic operations across up to 1,024 GPUs. The 200G 1.0 specification, released in April 2025, established a vendor-neutral foundation and since then, continued specification advancements have added additional features critical for production deployment in hyperscale environments. However, deployment requires broad ecosystem collaboration across hardware, software, and systems.
In this session, Astera Labs—a founding Board Member of the UALink Consortium—will join fellow panelists to discuss the practical challenges and breakthrough solutions behind deploying UALink at rack scale. Attendees will gain insight into recent specification updates, UALink’s security features and compliance considerations, memory semantics, protocol optimization, power and cost efficiencies, and the multi-vendor ecosystem driving this industry-wide transformation.
Panellists to be determined.