Gaurav Manocha | R&D Engineering, Sr Staff Engineer
Synopsys
Gaurav Manocha is a R&D Engineering, Sr Staff Engineer for PCIe/CXL Transactor Development at Synopsys, bringing over 13+ years of experience in the EDA industry. He has extensive expertise in CXL and PCIe generations, as well as background of simulation-to-emulation VIPs. Prior to his work in transactor development, Gaurav focused on VIP development for HPC protocols and specializes in developing robust verification strategies and system-level solutions for next-generation interconnect technologies. He has contributed to multiple PCIe features, including IDE ,TDISP, Flit Retry and presented at industry conferences such as PCI-SIG Developers Conference and Flash Memory Summit. He holds a Bachelor's degree in Electronics and Communication.
Appearances:
Future of Memory and Storage - Day 2 @ 10:20
PCIe Unordered I/O: Verification Pitfalls and System-Level Challenges
Unordered I/O (UIO) in PCI Express introduces a paradigm shift from traditional strong ordering, enabling higher bandwidth and lower latency for demanding applications. While UIO offers significant performance gains, it also presents unique verification and integration challenges.
This presentation delves into essential verification strategies for UIO, such as managing split completions, handling mixed PR-FC/NPR-FC traffic, configuring Virtual Channels (VCs), and ensuring secure operation with Integrity and Data Encryption (IDE). System-level considerations are addressed, including the risks of mixing UIO and non-UIO flows, particularly in peer-to-peer and multi-link environments.
Attendees will learn about the benefits and complexities of UIO, discover practical verification techniques, and receive actionable guidelines for integrating UIO into next-generation PCIe systems, ensuring robust and efficient adoption of this advanced feature.
Created by
Terrapinn is proud to be a member of isla.
Working together to build sustainable events