CHIH LONG Cheng | Senior Member of Technical Staff
Siemens EDA

Future of Memory and Storage - Day 2 @ 10:05

Demystifying Memory Sharing and Memory Pooling in LD-FAM devices

CXL Memory Pooling and Memory Sharing introduce multi-host, Fabric-Manager-driven dynamic capacity management — and with it, verification challenges that traditional single-host, point-to-point testbenches cannot catch. Issues such as shared-region coherency hazards under concurrent host access, data integrity violations in shared memory, and incorrect handling of dynamic allocation transitions are subtle yet critical. These gaps can silently pass through simulation and surface only in silicon.This paper presents a verification methodology designed to expose these hard-to-find bugs. We describe a deployment-realistic verification architecture for LD-FAM devices combining CXL Host, CXL Switch, and CXL Fabric Manager VIPs that mirrors actual multi-host data center topologies. We then walk through targeted verification scenarios: for Memory Pooling, dynamic partition allocation and de-allocation across hosts; for Memory Sharing, shared-region data integrity under concurrent multi-host access, rejection of invalid capacity requests, and coherency management flows that validate functional correctness beyond protocol compliance.

CHIH LONG Cheng, Senior Member of Technical Staff, Siemens EDA

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CHIH LONG Cheng / Demystifying Memory Sharing and Memory Pooling in LD-FAM devices

CHIH LONG Cheng, Senior Member of Technical Staff,
Siemens EDA

Alonso Cheng is a lead engineer on the CXL/PCIe VIP development team at Siemens, with over 10 years of experience in the EDA industry. He has contributed to the development and delivery of PCIe, and CXL VIPs and has played a key role in several high‑priority customer verification projects. In...

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