Berardino Carnevale is a Senior Technical Marketing and Product Manager at Rambus Security IP, focused on aligning security architectures with customer requirements and market needs for advanced semiconductor platforms. He works closely with engineering and customers to translate complex security capabilities into clear, deployable solutions for leading-edge technologies. Carnevale holds a PhD in secure embedded system design and began his career as a hardware designer before moving into system architecture and security certifications. His experience spans hardware security design, certification-driven development, and technical positioning across multiple market segments
Chiplet based architectures are transforming SoC design, but they also upend long standing security assumptions that were implicitly guaranteed by a monolithic die. By disaggregating a monolithic die into multiple, often multi-vendor chiplets, the implicit silicon trust boundary disappears, expanding the attack surface to include chiplet substitution, weak chiplet compromise, and exposed die to die interconnects. This discussion explores why traditional SoC security models do not scale to chiplet systems and introduces a system level security paradigm based on distributed trust with centralized authority.