Working as Director of Engineering at Samsung Semiconductor India Research Bangalore , having 20 +years of experience in Design Verification. Deep Expertise in Memory subsystems for DRAM [LPDDR,HBM] and UFS Flash Storage
The rapid proliferation of on-device AI and expanding frontier of edge computing are placing unprecedented demands on mobile flash storage architectures. Existing storage interfaces have become a critical bottleneck in realizing full potential of next gen AI platforms.This proposal presents a comprehensive deep dive and design verification challenges into recently released MIPI UniProv3.0 and MPHY HS-G6 which have served as the interconnect layer for JEDEC UFS, enabling high-performance, low-power flash storage across a broad range of devices. For the first time in mobile storage history PAM4 signaling come to MPHY HS-G6 with a leap of 46 Gbps per lane bandwidth which makes UFS5.0 not just an incremental update but a generational shift in unlocking speeds previously confined to datacenter SSDs now delivered with power and thermal envelope of a smartphone SoC. Sitting above the MPHY is UniProv3.0 with its redesigned Transport Frame Structure TFS, forward error correction (RS-FEC), 64-bit cyclic redundancy check (CRC), TFS data scrambling, gray coding, precoding and lane alignment features to operate at a bit error rate (BER) of less than 10-22 at the application layer.