Vatsal Patel | Senior Principal Software Engineer
Cadence Design Systems
Having 14+ years of experience in ASIC industry, mainly in verification, with key accomplishment of GDDR, HBM memory protocol expert. Other key works in Ethernet, AMBA, MIPI CSI-DPhy, Bluetooth. Leading team to develop complete verification IPs.
Appearances:
Future of Memory and Storage - Day 3 @ 09:05
Mastering HBM Verification: A Comprehensive Framework for Efficiency and Accuracy
High Bandwidth Memory (HBM) has emerged as a critical enabler for artificial intelligence (AI) workloads, offering the massive bandwidth and low power consumption necessary to meet the growing computational demands of deep learning and high-performance computing. HBM is a pivotal piece of technology for AI training as well as AI inference due to its high bandwidth and comparable low latency, which enables speedy data access and its processing, helping in overseeing the large datasets and performing complex calculations. With AI models continuously expanding in complexity, efficient verification methodologies for HBM devices are essential to ensure reliability and performance across various configurations. To meet this rising need, advanced verification methodologies must cover a wider operating range, increased use-cases, and more complex error scenarios.
Our approach significantly reduces Turn-Around Time (TAT) by meticulously generating testcase scenarios derived from both extensive in-house knowledge and real-time customer usage data, thereby making them exceptionally close to real-world operational conditions.
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